In flash memory products, it is common to design in functionality which supports concurrent operation between partitions or banks of flash memory. Each partition is typically a grouping of several blocks. Each block is individually accessible for program, eras, and read operations. Concurrent operation is dual operation in two different partitions simultaneously. For example, one block in one partition is being read which a different block in a different partition is being programmed or erased. Concurrency operations have been handled in the prior art by having an individual circuit for each partition, as is shown in the partition architecture 100 of FIG. 1. Partition 100 includes data sectors 102, and row drivers, column pass gates, predecoders, and timers 104. Sense amps are dedicated by partitions, and circuits 106 to program sense amplifiers for read operations and the like are all dedicated by partition. The circuits for each partition can program or read blocks in that partition. The circuits necessary for read and program operations are repeated for each partition block, such as partition blocks 202, 204, and 206 in a memory device such as device 200 shown in FIG. 2. A flash device with 16 partitions has 16 groupings of circuits, one for each partition, with each circuit individually capable of program or read operations as shown in FIG. 1.
FIG. 2 shows a memory 200 with 32 partitions. This memory 202 therefore has 32 program rows as well as 32 sense amp rows. Memories such as this can quickly become very large as density increases.
With concurrent operational memories requiring an individual circuit for each partition block, and with the increasing density of memories and therefore the increasing number of partitions and memory blocks of current memories, individual circuitry for each partition block can cause serious issues with respect to die size. Further, as memory densities continue to increase, such an architecture may effectively limit memory density to below that which is available in order to maintain die size.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory architecture that reduces real estate overhead in the memory, and improving functionality while maintaining die size.